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ISL90460
Single Volatile 32-Tap XDCPTM
Data Sheet October 7, 2005 FN8225.3
Digitally Controlled Potentiometer (XDCP)
The Intersil ISL90460 is a digitally controlled potentiometer (XDCP). Configured as a variable resistor, the device consists of a resistor array, wiper switches, a control section, and volatile memory. The wiper position is controlled by a 2-pin Up/Down interface. The potentiometer is implemented by a resistor array composed of 31 resistive elements and a wiper switching network. Between each element and at either end are tap points accessible to the wiper terminal. The position of the wiper element is controlled by the CS and U/D inputs. The device can be used in a wide variety of applications including: * LCD contrast control * Parameter and bias adjustments * Industrial and automotive control * Transducer adjustment of pressure, temperature, position, chemical, and optical sensors * Laser Diode driver biasing * Gain control and offset adjustment
Features
* Volatile Solid-State Potentiometer * 2-pin UP/DN Interface * DCP Terminal Voltage, 2.7V to 5.5V * Tempco 35ppm/C Typical * 32 Wiper Tap Points * Low Power CMOS - Active current 25A max. - Supply current 0.3A * Available RTOTAL Values = 10k, 50k, 100k * Temp Range -40C to +85C * Packages - 5 Ld SC-70, SOT-23 * Pb-Free Plus Anneal Available (RoHS Compliant)
Pinout
ISL90460 (5 LD SOT-23, SC-70) TOP VIEW
VDD RH
GND
U/D
CS
Ordering Information
PART NUMBER ISL90460WIE527-TK ISL90460WIE527Z-TK (See Note) ISL90460WIH527-TK ISL90460UIE527-TK ISL90460UIE527Z-TK (See Note) ISL90460UIH527-TK ISL90460UIH527Z -TK (See Note) ISL90460TIE527-TK ISL90460TIE527Z-TK (See Note) ISL90460TIH527-TK ISL90460TIH527Z-TK (See Note) PART MARKING AJM DDY AJV AJN DDW AJX DDX AJO DDU AJW DDV 100 50 RTOTAL (K) 10 TEMP RANGE (C) -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 PACKAGE (Tape and Reel) 5 Ld SC-70 5 Ld SC-70 (Pb-free) 5 Ld SOT-23 5 Ld SOT-23 (Pb-free) 5 Ld SC-70 5 Ld SC-70 (Pb-free) 5 Ld SOT-23 5 Ld SOT-23 (Pb-free) 5 Ld SC-70 5 Ld SC-70 (Pb-free) 5 Ld SOT-23 5 Ld SOT-23 (Pb-free) PKG. DWG. # P5.049 P5.049 P5.046 P5.046 P5.049 P5.049 P5.046 P5.046 P5.049 P5.049 P5.046 P5.046
ISL90460WIH527Z -TK (See Note) DDZ
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL90460 Block Diagram
VCC
Pin Descriptions
SOT-23/SC-70 5-PIN 1
RH
SYMBOL VDD GND U/D CS RH
DESCRIPTION Supply voltage Ground Up - Down Chip select High terminal/Wiper terminal
UP/DOWN (U/D) CONTROL AND MEMORY DEVICE SELECT (CS)
2 3 4 5
GND (GROUND) GENERAL
2
FN8225.3 October 7, 2005
ISL90460
Absolute Maximum Ratings
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Voltage on CS, U/D and VCC with Respect to GND . . . . -1V to +7V Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . . 300C IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6mA Power Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1mW
Recommended Operating Conditions
Temperature Range (Industrial) . . . . . . . . . . . . . . . . . . -40C to 85C Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
CAUTION: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Potentiometer Specifications Over recommended operating conditions unless otherwise stated
SYMBOL RTOT PARAMETER End to end resistance W version U version T version VR RH, RL terminal voltages Noise RW IW Wiper Resistance Wiper Current Resolution Absolute linearity (Note 1) Relative linearity (Note 2) RTOTAL temperature coefficient CH/CL/CW NOTES: 1. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage = (RH(n)(actual) - RH(n)(expected)) = 1 Ml Maximum. n = 1 .. 29 only. 2. Relative linearity is a measure of the error in step size between taps = RH(n+1) - [RH(n) + Ml] = 0.5 Ml, n = 1 .. 29 only. 3. 1 Ml = Minimum Increment = RTOT/31. 4. Typical values are for TA = 25C and nominal supply voltage. Potentiometer capacitances See equivalent circuit RH(n)(actual) - RH(n)(expected) RH(n+1) - [RH(n)+MI] 35 10/10/25 1 Ref: 1kHz CONDITIONS MIN 8 40 80 0 -120 600 0.6 32 1 0.5 TYP (Note 4) 10 50 100 MAX 12 60 120 VCC UNIT k k k V dBV mA Taps MI (Note 3) MI (Note 3) ppm/C pF
Equivalent Circuit
RTOTAL RH CH CW CL RL
RW
3
FN8225.2 FN8225.3 October 6, 2005 June 7,
ISL90460
DC Electrical Specifications
SYMBOL ICC ISB ILI ILI VIH VIL CIN Over recommended operating conditions unless otherwise specified. TEST CONDITIONS CS = 0V, U/D = fclock = 1MHz and VCC = 3V CS = VCC, U/D = VSS or VCC = 3V VIN = VSS to VCC VIN = VSS to VCC VCC x 0.7 VCC x 0.3 VCC = 3V, VIN = VSS, TA = 25C, f = 1MHz 10 0.3 MIN TYP (Note 4) MAX 25 1 1 1 UNIT A A A A V V pF
PARAMETER VCC active current (Increment) Standby supply current CS input leakage current U/D input leakage current CS, U/D input HIGH voltage CS, U/D input LOW voltage CS, U/D input capacitance
Timing Specifications
SYMBOL tCU tCI tIC tlL tlH fTOGGLE tSETTLE U/D to CS setup CS to U/D setup CS to U/D hold U/D LOW period U/D HIGH period
Over recommended operating conditions unless otherwise specified) (Figures 1 and 2) PARAMETER MIN 25 50 25 300 300 1 1 TYP (Note 4) MAX UNIT ns ns ns ns ns MHz s
Up/Down toggle rate Output settling time
CS tCU tIL
tIC
U/D tCI
tIH
tSETTLE
RH
FIGURE 1. SERIAL INTERFACE TIMING DIAGRAM, INCREMENT
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FN8225.3 October 7, 2005
ISL90460
CS tCU tIH U/D tCI RH tIL tSETTLE tIC
FIGURE 2. SERIAL INTERFACE TIMING DIAGRAM, DECREMENT
Pin Descriptions
RH
The ISL90460 contains a digital potentiometer connected as a rheostat or variable resistor. The wiper and one terminal of the digital potentiometer is tied to the RH pin, and the other terminal of the potentiometer is tied to the ground pin (GND). The resistance from the RH pin to ground will vary with the potentiometer setting; at the highest setting, the resistance will be the maximum (Rtot), at the lowest setting it will be a minimum.
Principles of Operation
There are two sections of the ISL90460: the input control, counter and decode section; and the resistor array. The input control section operates just like an up/down counter. The output of this counter is decoded to turn on a single electronic switch connecting a point on the resistor array to the wiper output. The resistor array is comprised of 31 individual resistors connected in series. At either end of the array and between each resistor is an electronic switch that transfers the connection at that point to the wiper. The wiper is connected to the RH terminal, forming a variable resistor from RH to GND. The direction of the wiper movement is defined when the device is selected. If during CS transition from High to Low the U/D input is LOW, the wiper will move down on each rising edge of U/D toggling. Similarly, the wiper will move up on each rising edge of U/D toggling if, during CS transition from High to Low, the U/D input is High. The wiper, when at either fixed terminal, acts like its mechanical equivalent and does not move beyond the last position. That is, the counter does not wrap around when clocked to either extreme. If the wiper is moved several positions, multiple taps are connected to the wiper for tSETTLE (U/D to RH change). The 2-terminal resistance value for the device can temporarily change by a significant amount if the wiper is moved several positions.
Up/Down (U/D)
The U/D input controls the direction of the wiper movement and whether the counter is incremented or decremented.
Chip Select (CS)
The device is selected when the CS input is LOW. The current counter value is stored in volatile memory when CS is returned HIGH. When CS is high, the device is placed in low power standby mode.
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FN8225.2 FN8225.3 October 6, 2005 June 7,
ISL90460 Small Outline Transistor Plastic Packages (SOT23-5)
D
P5.064
VIEW C
e1
5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE INCHES MILLIMETERS MIN 0.90 0.00 0.90 0.30 0.30 0.08 0.08 2.80 2.60 1.50 MAX 1.45 0.15 1.30 0.50 0.45 0.22 0.20 3.00 3.00 1.70 6 6 3 3 4 NOTES -
5 E 1 2 3
4 C L C L E1
SYMBOL A A1 A2 b b1
MIN 0.036 0.000 0.036 0.012 0.012 0.003 0.003 0.111 0.103 0.060
MAX 0.057 0.0059 0.051 0.020 0.018 0.009 0.008 0.118 0.118 0.067
e
C L 0.20 (0.008) M C L C
b
C
c c1 D E E1
A
A2
A1
SEATING PLANE -C-
e e1 L L1
0.0374 Ref 0.0748 Ref 0.014 0.022
0.95 Ref 1.90 Ref 0.35 0.55
0.024 Ref. 0.010 Ref. 5 0.004 0.004 0o 0.010 8o
0.60 Ref. 0.25 Ref. 5 0.10 0.10 0o 0.25 8o Rev. 2 9/03 5
0.10 (0.004) C
L2 N
WITH PLATING c
b b1 c1
R R1
NOTES:
BASE METAL
1. Dimensioning and tolerance per ASME Y14.5M-1994.
4X 1 R1 R GAUGE PLANE SEATING PLANE C L1 4X 1 VIEW C L
2. Package conforms to EIAJ SC-74 and JEDEC MO178AA. 3. Dimensions D and E1 are exclusive of mold flash, protrusions, or gate burrs. 4. Footlength L measured at reference to gauge plane. 5. "N" is the number of terminal positions. 6. These Dimensions apply to the flat section of the lead between 0.08mm and 0.15mm from the lead tip. 7. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only.
L2
6
FN8225.3 October 7, 2005
ISL90460 Small Outline Transistor Plastic Packages (SC70-5)
D
P5.049
VIEW C
e1
5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE INCHES MILLIMETERS MIN 0.80 0.00 0.80 0.15 0.15 0.08 0.08 1.85 1.80 1.15 MAX 1.10 0.10 1.00 0.30 0.25 0.22 0.20 2.15 2.40 1.35 6 6 3 3 4 NOTES -
5 E 1 2 3
4 C L C L E1
SYMBOL A A1 A2 b b1
MIN 0.031 0.000 0.031 0.006 0.006 0.003 0.003 0.073 0.071 0.045
MAX 0.043 0.004 0.039 0.012 0.010 0.009 0.009 0.085 0.094 0.053
e
C L 0.20 (0.008) M C L C
b
c c1
C
D E E1
A
A2
A1
SEATING PLANE -C-
e e1 L L1
0.0256 Ref 0.0512 Ref 0.010 0.018
0.65 Ref 1.30 Ref 0.26 0.46
0.017 Ref. 0.006 BSC 0o 5 0.004 0.004 0.010 8o
0.420 Ref. 0.15 BSC 0o 5 0.10 0.15 0.25 8o
0.10 (0.004) C
L2
WITH PLATING c b b1 c1
5
N R R1 NOTES:
Rev. 2 9/03
BASE METAL
1. Dimensioning and tolerances per ASME Y14.5M-1994.
4X 1 R1 R GAUGE PLANE SEATING PLANE C L1 4X 1 VIEW C L
2. Package conforms to EIAJ SC70 and JEDEC MO-203AA. 3. Dimensions D and E1 are exclusive of mold flash, protrusions, or gate burrs. 4. Footlength L measured at reference to gauge plane. 5. "N" is the number of terminal positions. 6. These Dimensions apply to the flat section of the lead between 0.08mm and 0.15mm from the lead tip. 7. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only.
L2
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 7
FN8225.3 October 7, 2005

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